Digital / Mixed - Signal Design Verification Engineer

Elsys Eastern Europe d.o.o.  •  Beograd  • Rok: 24.05.2017

Highly motivated, well organized and dynamic engineer, 2+ year of experience with verification methodologies – UVM, Specman/eRM, Strong background in digital electronics, ASIC/FPGA (pročitaj oglas)

Verification Engineer

RT-RK d.o.o.  •  Novi Sad  • Rok: 21.05.2017

A minimum of 1 year of experience in the following areas: Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC, Hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL.. Scripting (pročitaj oglas)

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