Verification Engineer

RT-RK d.o.o.  •  Novi Sad  • Rok: 21.05.2017

A minimum of 1 year of experience in the following areas: Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC, Hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL.. Scripting (pročitaj oglas)

Prikaži i one oglase čiju ažurnost sajt HelloWorld.rs ne može u potpunosti da garantuje

Prikaži još 1 takav oglas

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